ASML continues to rise: AI compute absorbs lithography, High-NA enters commercial production

In plain terms ASML has once again raised its 2026 forecasts, driven by demand for AI chips. In the wake of this, Intel becomes the first customer to put a High-NA EUV line into commercial production, on the Panther Lake chips. The capacity pinch we were following at the packaging level at TSMC has moved up a notch: it is now lithography that is in command.

The context

ASML had already raised its 2026 forecast earlier in the year, on the strength of EUV orders. Since the spring, the thesis of a slowdown in the memory cycle had been putting pressure on the trajectory. The T2 statement puts this thesis to rest: AI demand compensates for memory, EUV orders remain steady. Intel confirms in the wake of this the commercial production of the High-NA EXE:5000 line for Panther Lake.

The data

• According to Tech in Asia (15/07/26), ASML raises its 2026 midpoint again, citing continued demand for EUV machines.
• ETNews (15/07/26) headlines on an ASML T2 surprise that puts the memory slowdown thesis on hold, market-side.
• Still according to Tech in Asia (15/07/26), Intel operates the first High-NA EXE:5000 line in commercial production on Panther Lake; ASML announces this class of machine at more than 185 wafers/hour, targeting HVM 2025-2026.

Under the hood

The High-NA (numerical aperture 0.55, versus 0.33 in Low-NA) allows high-resolution patterning in a single exposure on the thinnest critical layers. In Low-NA, these same layers often require multi-patterning - two or three sequential passes per layer. Switching a critical layer to High-NA eliminates these passes: fewer masks, fewer alignments, effective throughput increase in the fab - which rationalizes the strength of ASML's raised guides.

Scenarios & Risks

Base scenario: the EUV backlog remains under pressure until mid-2027; AI compensates for memory in ASML's mix. Bear scenario: if the memory cycle weakens faster than anticipated, ASML's product mix deteriorates in the second half, independently of AI demand. Execution risk: High-NA reliability in HVM (particulate contamination, uptime over several months) remains to be demonstrated on long Intel runs, before other foundries dare to try.

So what

The AI compute wall has changed floors. TSMC was concentrating the bottleneck of advanced nodes; ASML is now the upstream bottleneck. For a CIO or founder budgeting for 2027, don't bet on a decrease in GPU costs until the EUV line has caught up with the backlog. And watch the next EXE:5000 orders: they will tell if High-NA remains an Intel bet or becomes an industry standard.