Samsung pushes HBM5 base die to 2nm targeting +50% speed - the memory war moves to logic-class nodes

Samsung plans to build the base die of HBM5 using its 2nm process, aiming for a 50% speed improvement. Memory is no longer just about increasing capacity; it's also about leveraging advanced logic-node economics.

In plain terms - Samsung will build the base die of its next-generation HBM5 memory on its 2nm GAA process node - a logic-class node - to hit a 50%+ speed uplift over HBM4E.

Le fait

ETNews reports (27 July 2026) that Samsung is pushing HBM5 base die to a 2nm gate-all-around (GAA) process. Koo Ja-geum, VP at Samsung's Foundry Business, said via the company newsroom that HBM5 is expected to need a 50%+ speed uplift over its immediate predecessor HBM4E, and that the base die's node choice is driven by both speed and power efficiency. Tech in Asia corroborates the 50%+ vs HBM4E framing. HBM5 succeeds HBM4E (itself a step beyond HBM4), which is still in ramp phase across SK Hynix / Samsung / Micron.

Notre lecture

The base die is the logic layer that sits under stacked DRAM dies and orchestrates the interface with the GPU. Historically it was built on trailing-edge nodes because DRAM economics dominated. Moving base die to 2nm GAA - the same node used for leading logic chips - signals two things: (1) HBM interface bandwidth is now the binding constraint, not capacity; (2) Samsung is willing to spend logic-node wafers on memory, which reshapes fab allocation across foundries.

À surveiller

• SK Hynix response on base-die node choice
• TSMC vs Samsung Foundry share for 2nm base die
• Whether Nvidia / AMD roadmap dates pull HBM5 forward or leave it as 2027-2028 supply